Fujitsu Semiconductor Introduces Top Customized SoC Innovation Design Methodology
Shanghai, January 15, 2014 – Fujitsu Semiconductor (Shanghai) Co., Ltd. today announced the successful development of a new design methodology tailored for advanced 28 nm SoC devices that not only enables higher circuit densities, but also Effectively reduce development time. A new design approach can increase the density of the circuit by 33% and reduce the final line layout time to one month. This design approach will be integrated into Fujitsu Semiconductor's new custom SoC designs to help customers develop RTL-Handoff SoC devices. Fujitsu Semiconductor expects to begin accepting SoC orders using this new design method since February 2014.
SoC devices that use a top-of-the-line process such as 28 nm require more and more functions and performance, and more and more circuits must be built into the chip. In the future, the design of SoC will become more and more complex, and the development time will increase as compared with the past. At the same time, how to effectively solve the power consumption problem has become a greater challenge for designers.
In response to increasingly complex SoC designs, Fujitsu Semiconductor has developed innovative design methods that enable higher circuit density, shorter development time and lower power consumption, and are integrated into Fujitsu Semiconductor's new custom SoC designs. Helping customers develop RTL-Handoff SoC components. Compared with the traditional design process, designers can use Fujitsu Semiconductor's new design method to increase the circuit size by 33% in the same size chip, and reduce the final line layout time to one month.
New design method effectively minimizes White Space
The new exclusive design process estimates the floor plan that is easier to route and optimizes for the internal data bus based on routing paths and timing closure. These design steps minimize the number of White Spaces that cannot be built into transistors, allowing the chip to accommodate more circuitry.
Coordinating logic and physical architecture through patented technology
This patented technology automatically synthesizes netlist data for physical routing without any logic design, and improves the overall design routing efficiency and makes timing closure easier, thus reducing the time required for the final routing process. , to achieve higher density integration.
Figure 1: Schematic diagram of Fujitsu Semiconductor's new customized SoC design methodology
Fujitsu Semiconductor is a world-class ASIC supplier. Through years of experience and expertise in the industry, Fujitsu Semiconductor continues to provide a complete, customized SoC solution that combines advanced design and manufacturing services. And system level research, development support and other services. Through the above solutions, Fujitsu Semiconductor will be able to support customers to quickly develop high performance and power saving SoC devices.
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