Project Background and Feasibility Analysis

Project Name: High-Speed Network Intrusion Detection System Based on SNORT Rule Set

Application Background

The misuse-based intrusion detection system (IDS) is currently one of the most widely used network security solutions. These systems are known for their high accuracy in detecting known threats and a relatively low false positive rate. They rely on a database of pre-defined attack signatures, which are accumulated from past network attacks and system vulnerabilities. By matching incoming traffic against these predefined patterns, they can identify potential threats. As such, the pattern library and pattern matching engine are at the core of these systems.

However, with the rapid growth of network speeds, traditional misuse-based IDSs have begun to show significant performance limitations. Their ability to detect malicious traffic has declined, and they consume more system resources, especially when the signature database expands. In high-load environments, these systems may even drop some packets to maintain performance, which compromises their overall effectiveness and reliability.

The main limitation in the performance of misuse-based IDSs lies in the efficiency of the pattern matching engine. This component processes network packets by comparing them against regular expressions that define intrusion patterns. In many systems, such as Snort, these patterns are represented using regular expressions stored in the rule base. According to reference [1], over 90% of CPU usage in misuse-based IDSs comes from regular expression matching. Therefore, this project focuses on developing a high-speed network intrusion detection system based on the SNORT rule set, aiming to overcome these performance bottlenecks.

Research Status

To improve the efficiency of pattern matching, software-based engines often employ multi-pattern matching algorithms. Reference [2] highlights that most modern regular expression matching techniques are based on the Aho-Corasick algorithm, an optimized version of the Generalized Aho-Corasick (GAC). The design of GAC is detailed in [3]. However, when constructing a Deterministic Finite Automaton (DFA) from a Non-deterministic Finite Automaton (NFA), the number of states increases exponentially, leading to higher memory consumption and limiting the size of the regular expressions that can be processed efficiently.

In hardware-based pattern matching, both NFA and DFA approaches are commonly used. Reference [4] introduces a new structure that enhances state density through compression coding. Meanwhile, [5] proposes a method that reduces memory usage by up to 95% by applying graph theory algorithms to optimize DFA transitions. However, these methods still face challenges due to limited hardware resources. The exponential growth in DFA states makes it difficult for current FPGA platforms to handle large-scale regular expression matching tasks.

In [6], the first FPGA-based regular expression matching engine using the NFA mechanism was introduced. It allows one character to be matched per cycle and presents several modular design approaches. This project builds upon that idea, improving the NFA-based architecture to eliminate data backtracking issues. The proposed system uses a modular design to create a high-speed, data-driven hardware matching engine.

Main Content

This project addresses the key performance bottleneck in traditional software-based intrusion detection systems—regular expression pattern matching. It aims to develop a high-speed network intrusion detection system based on the SNORT rule set. The system consists of three main components: the design and implementation of a hardware-based regular expression pattern matching engine (as a hardware accelerator), the underlying hardware transmission platform, and the software stack (including drivers and applications) built around the SNORT rules.

Key Technologies and Innovations

(1) Design of a multi-pattern matching hardware engine for regular expressions;

(2) Development of a communication platform based on PCI-E interface between CPU and FPGA;

(3) Implementation of hardware-based network packet capture;

(4) Design of the software driver for system integration and control.

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