Evaluation of processing technology for system-on-chip integration

SoC devices with multiple processing units are currently an important part of the product design chain. This article combines various factors to evaluate the advantages and disadvantages of different processing units, and through the design examples of satellite radio receivers to help developers understand the complex balance between SoC processing tasks involved and effectively master the division of system functions.

When preparing for the development of increasingly complex portable systems, one of the biggest challenges facing designers is to use what kind of processor combination to achieve the optimal "3P" index, namely the highest system performance, the lowest price and power consumption The smallest. System-on-chip (SoC) integration makes today's innovation possible, but it often involves combining different processor units on a single device. These units may include programmable functions such as general-purpose microprocessors (usually RISC), DSPs, FPGAs, and accelerators, and may also have fixed-function accelerators. Since these units can be obtained in the form of dedicated devices, it is quite difficult for designers to conduct a comprehensive performance evaluation among them and then decide to use them in the most effective way.

Analysis of the advantages and disadvantages of the processing unit

Before implementing multi-core processors, it was relatively simple to choose between RISC and DSP. If a large amount of system processing work is related to data, then use RISC, even if the signal processing will suffer some losses. If a lot of processing work is related to the signal, then use DSP and strive to obtain unsatisfactory control and data processing performance. But for multi-core integration, considering the addition of other processing units, this type of selection becomes very complicated. The correct answer is not entirely technical, but should be based on optimization flexibility, ease of use, cost, power consumption and performance.

The basic advantages and disadvantages of various processing units are summarized in Table 1. The general-purpose RISC processor is optimized for data processing, it is easy to use and flexible, and its cost, power consumption and performance are all acceptable. DSPs are optimized for real-time signals. The power consumption and cost of processing real-time signals is usually lower than RISC, but they are often more difficult to use.

Programmable accelerators or semi-programmable processors can be designed for data or signal processing. An example is the Viterbi processor used in communication systems. It is fully programmable for Viterbi encoding or decoding, but it is useless for any other function. In terms of its function, the cost and power consumption of a programmable accelerator is always lower than that of RISC or DSP, and its performance is higher, but in essence, it is slightly less flexible, more difficult to use, and has bugs. The tolerance is low and not easy to change.

Fixed-function accelerators (usually ASICs) used for data or signal processing can only perform a specific function. Fixed-function accelerators are always the lowest cost, lowest power, and highest performance solutions, but they lack any degree of flexibility. Once the ASIC is designed and debugged, it will become very easy to use in the hands of system developers. However, its design and debugging are very difficult compared with programmable devices, and it is impossible to reprogram in the future.

Divide system processing functions

Although making decisions among various processing units is a complex task, there is a feasible selection procedure that divides various system functions into various processing units. Mapping the processing requirements of a system to an existing multi-core SoC is different from creating a new multi-core SoC by mapping processing requirements. However, the process is similar.

In order to map the system to an existing SoC, the system designer must determine the details of the system solution and the market it targets. This includes product features and algorithm components, as well as adding features and bug-solving strategies, whether during design or throughout the life of the product. Once these details are determined, the system function must be determined as a signal or data processing task, and then divided into three different categories:

Features that are clear and will remain the same: These features include discrete cosine transform (DCT) or fast Fourier transform (FFT), they will not change any more, and have been out long enough, so all bugs have been eliminated. These functions use fixed function accelerators or optimization.

Features that are clear but subject to change: These features have a certain degree of flexibility. For example, although a single FFT can be processed by an ASIC, the ability to reassemble multiple related FFTs into a series of implementations will require a programmable accelerator.

Uncertain and variable new functions: The processor units that meet these needs are programmable RISC, DSP and FPGA. Although designers may not know what these uncertainties or new features are, it is necessary to measure the approximate performance and memory required to meet the anticipated requirements.

When system functions have been broken down into these three categories, the system can be mapped to an existing SoC device. The whole procedure is divided into the following steps:

1. Determine the complete list of features and functions of the final system. If possible, including estimates of new features and functions, they can be added at any time during the life of the product using the SoC.

2. The feature and function list is divided into a data processing part and a signal processing part.

3. Divide the functions in each list (data and signals) into three categories: a. Functions that are clear and will remain unchanged during the life of the product; b. Functions that are clear but allow certain changes during the life of the product c. Uncertain and changeable new functions.

4. Estimate the performance required for each item in each list.

5. Estimate the memory required for each item in each list.

6. Assignment: a. Appropriate clear functions to feasible fixed-function accelerators; b. Remaining clear functions to feasible programmable accelerators; c. Uncertain and variable new functions to appropriate programmable devices (RISC for data processing , DSP for signal processing).

The goal of the last step is to use accelerators as much as possible, and leave flexibility and margin to the programmable unit. Obviously, the assignment of clear, variable and uncertain functions depends to a certain extent on what hardware the relevant SoC can provide. Mapping a system to a new SoC instead of an existing SoC may cause longer product planning time, so the problem that the designer must solve will often be related to a series of products based on the new device. Designers need to determine which algorithm components are better understood, and there are no defects or changes; they also need to determine which parts of the system may change during the entire design period or product line. When it comes to function assignment (step 6), the designer of a new scheme can very definitely assign a clear function (step 3 a) to a fixed functional unit, and a somewhat changed function (step 3 b) can be assigned to Program the accelerator to assign uncertain, changing new functions (step 3 c to the RISC that processes data and the DSP that processes signals).

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