The role and design skills of PCB layer stacking in PCB layout in controlling EMI radiation
There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coatings, selecting suitable EMI suppression components, and EMI simulation designs. This article starts from the most basic PCB layout, discusses the role and design skills of PCB layered stacking in controlling EMI radiation.
Power bus
Properly placing a capacitor of appropriate capacity near the power supply pin of the IC can make the output voltage of the IC jump faster. However, the problem is not here. Due to the finite frequency response of the capacitor, this makes it impossible for the capacitor to generate the harmonic power required to cleanly drive the IC output over the full frequency band. In addition, the transient voltage developed on the power bus forms a voltage drop across the inductor of the decoupling path, which is the primary source of common-mode EMI interference. How should we solve these problems?
As far as the ICs on our boards are concerned, the power plane around the IC can be thought of as an excellent high-frequency capacitor that collects the energy that is leaked by discrete capacitors that provide high-frequency energy for clean outputs. In addition, the excellent power supply layer has a small inductance, so that the transient signal synthesized by the inductor is also small, thereby reducing common mode EMI.
Of course, the wiring from the power plane to the IC power supply pin must be as short as possible because the rising edge of the digital signal is getting faster and faster, preferably directly to the pad where the IC power supply pin is located. This is discussed separately.
To control common-mode EMI, the power plane must be decoupled and have a low enough inductance. This power plane must be a well-designed pair of power planes. Someone may ask, to what extent is it good? The answer to the question depends on the layering of the power supply, the material between the layers, and the operating frequency (ie, the function of the rise time of the IC). Typically, the power supply is layered at 6 mils and the mezzanine is FR4. The equivalent capacitance per square inch of power plane is approximately 75 pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100 to 300 ps, ​​but according to the current development speed of ICs, devices with a rise time of 100 to 300 ps will occupy a high proportion. For circuits with 100 to 300 ps rise time, the 3 mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use a layering technique with a layer spacing of less than 1 mil and to replace the FR4 dielectric material with a material having a high dielectric constant. Ceramics and ceramics now meet the design requirements of 100 to 300 ps rise time circuits.
Although new materials and methods may be used in the future, for today's common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and make the transient signal low enough. That said, common mode EMI can be reduced very low. The PCB layered stack design example given here will assume a layer spacing of 3 to 6 mils.
Electromagnetic shielding
From the perspective of signal routing, a good stratification strategy should be to place all signal traces in one or several layers, which are next to the power or ground plane. For the power supply, a good stratification strategy should be that the power layer is adjacent to the ground plane, and the distance between the power plane and the ground plane is as small as possible. This is what we call the "layering" strategy.
PCB stacking
What kind of stacking strategy helps shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer, with single or multiple voltages distributed across different parts of the same layer. The case of multiple power planes is discussed later.
4-layer board
There are several potential problems with 4-layer board design. First, the conventional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer, the power supply and the ground layer are in the inner layer, the distance between the power supply layer and the ground layer is still too large.
If the cost requirement is first, consider the following two alternatives to traditional 4-layer boards. Both of these solutions improve EMI suppression performance, but only for applications where the on-board component density is low enough and there is sufficient area around the component to place the required copper layer on the power supply.
The first is the preferred solution. The outer layers of the PCB are all ground layers, and the middle two layers are signal/power layers. The power supply on the signal layer is routed with a wide line, which allows the path impedance of the supply current to be low and the impedance of the signal microstrip path to be low. From the perspective of EMI control, this is the best 4-layer PCB structure available. The outer layer of the second scheme takes the power and the ground, and the middle two layers take the signal. Compared with the traditional 4-layer board, the improvement is smaller, and the interlayer resistance is as poor as the traditional 4-layer board.
If you want to control the trace impedance, the above stacking scheme must be very careful to place the traces under the power and ground copper islands. In addition, the copper or copper islands on the ground should be interconnected as much as possible to ensure DC and low frequency connectivity.
6-layer board
If the density of the components on the 4-layer board is relatively large, it is preferable to use a 6-layer board. However, some laminate solutions in the 6-layer board design do not have a good shielding effect on the electromagnetic field, and have little effect on the reduction of the power bus bus transient signal. Two examples are discussed below.
In the first case, the power and ground were placed on the 2nd and 5th layers respectively. Due to the high impedance of the copper of the power supply, it is very disadvantageous for controlling the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.
In the second example, the power supply and the ground are placed on the 3rd and 4th layers respectively. This design solves the problem of the copper-clad impedance of the power supply. Due to the poor electromagnetic shielding performance of the first layer and the sixth layer, the differential mode EMI is increased. This design can solve the differential mode EMI problem if the number of signal lines on the two outer layers is the least and the trace length is short (shorter than the 1/20 of the highest harmonic wavelength of the signal). The suppression of differential mode EMI is particularly good when copper is filled with no components and no trace areas on the outer layer and the copper area is grounded (interval every 1/20 wavelength). As mentioned earlier, the copper area is connected to the internal ground plane at multiple points.
The general-purpose high-performance 6-layer board design generally lays the first and sixth layers as the ground layer, and the third and fourth layers take the power and ground. Since there are two layers of the centered double microstrip signal line layer between the power supply layer and the ground layer, the EMI suppression capability is excellent. The disadvantage of this design is that the trace layer has only two layers. As mentioned earlier, if the outer traces are short and copper is laid in the no trace area, the same stack can be achieved with a conventional 6-layer board.
Another 6-layer board layout is signal, ground, signal, power, ground, and signal, which enables the environment required for advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power layer and the ground layer are paired. Obviously, the downside is that the stacking of layers is unbalanced.
This usually causes troubles in manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. If the copper layer density of the third layer is close to the power layer or the ground layer after copper filling, the board can not be strictly regarded as a structurally balanced circuit board. . The copper filled area must be connected to power or ground. The distance between the connecting vias is still 1/20 wavelength, and it is not necessary to connect everywhere, but ideally it should be connected.
10-layer board
Since the insulating isolation layer between the multilayer boards is very thin, the impedance between the 10 or 12 layer circuit board layers and the layers is very low, and excellent signal integrity is completely expected as long as the layering and stacking are not problematic. It is difficult to process 12-layer boards at a thickness of 62 mils, and there are not many manufacturers that can process 12-layer boards.
Since the signal layer and the loop layer are always separated by an insulating layer, the scheme of distributing the middle 6 layers in the 10-layer board design to take the signal line is not optimal. In addition, it is important to have the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, and signal.
This design provides a good path for signal current and its loop current. The proper routing strategy is that the first layer is routed along the X direction, the third layer is routed along the Y direction, the fourth layer is routed along the X direction, and so on. Intuitively looking at the traces, the first layer 1 and the third layer are a pair of layered combinations, the fourth layer and the seventh layer are a pair of layered combinations, and the eighth layer and the tenth layer are the last pair of layered combinations. When it is necessary to change the direction of the trace, the signal line on the first layer should be changed direction by "via" to the third layer. In fact, it may not always be possible to do so, but as a design concept, try to comply as much as possible.
Similarly, when the direction of the signal is changed, it should pass through the vias from the 8th and 10th layers or from the 4th to the 7th. This routing ensures that the coupling between the forward path and the loop of the signal is tightest. For example, if the signal is routed on the first layer and the loop is on the second layer and only on the second layer, then the signal on the first layer is transferred to the third layer even by "via". The loop is still on the second layer, maintaining low inductance, large capacitance characteristics and good electromagnetic shielding performance.
What if the actual route is not the case? For example, the signal line on the first layer passes through the via hole to the 10th layer. At this time, the loop signal has to find the ground plane from the 9th layer, and the loop current needs to find the nearest ground via (such as the grounding pin of the component such as resistor or capacitor). . If there is such a via in the vicinity, it is really lucky. If no such via is available, the inductance will increase, the capacitance will decrease, and EMI will increase.
When the signal line must leave the current pair of wiring layers through the via to other wiring layers, the ground via should be placed near the via, so that the loop signal can be smoothly returned to the proper ground plane. For Layer 4 and Layer 7 layered combinations, the signal loop will be returned from the power or ground plane (ie, Layer 5 or Layer 6) because the capacitive coupling between the power and ground planes is good and the signal is easily transmitted. .
Multi-power layer design
If two power planes of the same voltage source need to output a large current, the board should be laid into two sets of power and ground planes. In this case, an insulating layer is placed between each pair of the power supply layer and the ground layer. This gives us two pairs of equal-impedance power buss that we want to divide the current. If the stack of power planes causes unequal impedances, the shunt is not uniform, the transient voltage will be much larger, and EMI will increase dramatically.
If there are multiple supply voltages with different values ​​on the board, multiple power planes are required accordingly. It is important to remember to create separate pairs of power and ground planes for different power supplies. In both cases, when determining the location of the paired power and ground planes on the board, remember the manufacturer's requirements for the balanced structure.
to sum up
Given that most engineers design boards that are 62 mils thick and have no blind vias or buried vias, the discussion of board delamination and stacking is limited to this. For boards with too much thickness difference, the layering scheme recommended in this paper may not be ideal. In addition, the processing method of the circuit board with blind holes or buried holes is different, and the layering method of this paper is not applicable.
The thickness, via process, and number of layers in the board design are not critical to solving the problem. Excellent layered stacking ensures bypass and decoupling of the power busbars and minimizes transient voltages on the power or ground plane. The key to shielding the signal and the electromagnetic field of the power supply. Ideally, there should be an insulating isolation between the signal trace layer and its return ground plane, and the matching layer spacing (or more than one pair) should be as small as possible. Based on these basic concepts and principles, it is possible to design a board that always meets the design requirements. Now, IC's rise time is already short and will be shorter, and the techniques discussed in this article are essential to address EMI shielding issues.
- The Description of 3G 4G LTE/5G Antenna
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2G base station: GSM: 900/1800MHz; CDMA: 800 MHZ;
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4G base station: TDD-LTE: 2320-2370,2570-2620MHz; -
This paper discusses the key technologies in 3G/4G/5G (third generation/fourth generation/fifth generation) communication systems, and then discusses the differences in the antenna technologies adopted by them. After reading and studying a large number of papers on the key technologies of 3G/4G/5G communication system, here I make some analysis and summary of my own. With the rapid development of science and technology, mobile communication technology has undergone profound changes, from 1G to 2G, to 3G, and then to 4G and 5G. On December 4, 2013, the fourth generation of mobile communication 4G technology was officially operated in the Chinese market, which means that China's mobile communication industry has entered the 4G era. At this time, research institutes in various countries and world-renowned enterprises engaged in communication technology research have entered the research and development of the new generation of mobile communications, namely 5G (fifth generation mobile communication system). No matter which generation of communication system, the research technology is to analyze the characteristics of wireless communication channel to overcome the noise interference. A lot of researchers are now looking at Massive MIMO technology. How is it different from the antenna technology used in 3G/4G communication systems? Will it become the core technology of the next generation of wireless communications? 1 Key technologies of 3G/4G/5G Communication System 1.1 Key technologies of 3G Communication System Since the early 1990s, the mobile communication industry began to actively study the standards and technologies of the third generation of mobile communication. In January 2009, China's Ministry of Industry and Information Technology issued 3G licenses to China Mobile, China Telecom and China Unicom, indicating that China entered the ERA of 3G mobile communications. The third generation mobile communication system mainly includes WCDMA, CD-MA2000 and TD-SCDMA. Its key technologies include: A. Rake receiving technology; B. Channel coding and decoding technology; C. Power control technology; D. Multi-user detection technology; E. Smart antenna; F. Software radio. 1.2 Key technologies of 4G Communication System In December 2013, China officially entered the era of 4G (fourth generation mobile communication system) communication network. In 4G mobile communication system, OFDM(Orthogonal frequency Division multiplexing) technology is adopted. OFDM technology is due to its spectrum utilization
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It is widely regarded as high rate of 2 and good anti-multipath fading performance. In the future, RESEARCH related to OFDM technology will also be carried out in 5G communication networks. The main key technologies of 4G communication system include: a. OFDM technology; B. MIMO technology; C. Multi-user detection technology; D. Software radio; E. Smart antenna technology; F. IPv6 technology. China's Ministry of Industry and Information Technology has just issued 4G licenses to the three major operators, and they are still deploying their networks on a large scale with a small number of users. At this time, China Mobile said it will start the RESEARCH and development of 5G communication system. Analysts pointed out that the three major operators are participating in THE RESEARCH and development of 5G, one is to keep up with the changes of The Times, and the other is that the demand is faster than the technology development. Li Zhengmao, vice-president of China Mobile, said at the 2014 MWC in Barcelona: "China Mobile will fully support the development of 5G projects, hoping to lead the industry in THE development of 5G technology and the setting of technical standards." With the deepening of mobile communication technology research, the key support technologies of 5G will be gradually defined and enter the substantive standardization research and formulation stage in the next few years. The jury is still out on what core technologies will be used in the future. However, I have compiled a list of nine key technologies that have been the focus of discussion in various high-end mobile forums. A. Large-scale MIMO technology; B. Filter bank based multi-carrier technology; C. Full duplex technology; D. Ultra-dense heterogeneous network technology; E. Self-organizing network technology; F. Use of high frequency band; G. Software-defined wireless networks; H. Wireless access technology: (1) BDMA (Beam Split multiple Access technology)
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3 (2) NOMA (Non-orthogonal multiple Access technology) i. D2D (device-to-device) communication. Figure 1 is the layout of Massive MIMO antennas in 5G communication networks. I am studying Massive MIMO technology in my lab. Figure 1 shows users communicating with each other centered on a large-scale antenna. The performance of wireless communication systems is mainly restricted by mobile wireless channels. Wireless channel is very complex, and its modeling has always been a difficult point in system design. Generally, statistics are made according to the measured values of communication systems in specific frequency bands. Wireless fading channel is divided into large scale fading channel model and small scale fading channel model. The so-called large-scale fading model describes the field intensity variation over a long distance (hundreds or thousands of meters) between the transmitter and receiver, and reflects the rule that the received signal power changes with the distance caused by path loss and shadow effect. A small scale fading model describes the rapid fluctuations of the received field intensity over a short distance or time. The large scale fading channel model is caused by the influence of the surface contour (such as mountains, forests, buildings, etc.) between the receiver and the source. The small-scale fading channel model is caused by the multipath effect and doppler effect. If there are a large number of reflected paths but no LOS (direct signal) signal component, the small-scale fading is called Rayleigh fading, and the envelope of the received signal is described statistically by the Rayleigh probability density function. If LOS is present, the envelope is subject to Rician distribution. Multipath effect phenomena cause flat fading and frequency selective fading.
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