7 Series FPGA Frame ECC Logic How to Check Unit or Double Position Errors in Configuration Frame Data
The 7 Series FPGA Frame ECC logic is designed to detect single or double-bit errors in the configuration frame data. It employs a 13-bit Hamming code, which is generated during the BitGen process based on the frame data. This mechanism ensures that any bit-level corruption can be identified and potentially corrected.
During the readback process, the Frame ECC logic computes a composite value using all the bits within the frame, including the ECC bits themselves. If no changes have occurred, or if the original values are still intact, the SYNDROME[12:0] will be zero. However, if any bit—whether it's part of the data or the ECC bits—changes, the position of the error is indicated by the SYNDROME[11:0]. In the case of two bit errors, SYNDROME[12] will be zero, while the remaining bits will be non-zero. If more than two bits change, the syndrome becomes undefined.
When one or two bits are corrupted, the FRAME_ECC module can assert an error output. To enable this functionality, the FRAME_ECC_VIRTEX6 primitive must be instantiated in the user design and accessed through interfaces like SelectMAP, JTAG, or ICAP.
At the end of each readback frame, the syndrome_valid signal is asserted for one cycle of the readback clock (CCLK, TCK, or ICAP_CLK). The number of cycles required for a full readback depends on the interface used. Correcting a changed bit requires user intervention, as the FRAME_ECCE2 logic itself does not perform automatic correction. Therefore, the design must either store the original frame data or be capable of retrieving it for reloading.
The simplest operation involves reading a frame via ICAP into the module’s RAM. Once the frame is stored, if an error is detected, the readback stops, and the syndrome is saved. If SYNDROME[12] is 0 and SYNDROME[11:0] is non-zero, the entire frame must be restored. If SYNDROME[12] is 1, the error location can be determined using SYNDROME[11:0]. After correction, the frame is written back to its original address, and readback resumes at the next frame.
**Pin Names and Descriptions:**
- **SYNDROMEVALID**: Output. Indicates when the syndrome is valid for sampling.
- **ECCERROR**: Output. Indicates whether an error was detected.
- **SYNDROME[12:0]**: Output. Provides the syndrome value for error detection.
- **CRCERROR**: Output. Indicates a CRC error during readback.
- **FAR[25:0]**: Output. Frame address register value.
- **SYNWORD[6:0]**: Output. Indicates the word address where the error occurred.
- **SYNBIT[4:0]**: Output. Indicates the specific bit within the word that has an error.
- **ECCERRORSINGLE**: Output. Indicates a single-bit error.
For SSIT devices, FRAME_ECCE2 is available across all SLRs. It is recommended to place and use this component on each SLR to ensure comprehensive ECC coverage. If only one FRAME_ECC is present and no layout is defined, it will be placed in the main SLR by default.
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