7 Series FPGA Frame ECC Logic How to Check Unit or Double Position Errors in Configuration Frame Data
The Frame ECC logic in the 7 Series FPGA is designed to detect single or double-bit errors in configuration frame data. It employs a 13-bit Hamming code, which is generated during the BitGen process based on the frame data. This error-checking mechanism ensures data integrity during configuration and readback operations.
During the readback process, the Frame ECC logic calculates a composite value that includes all bits of the frame, including the ECC bits themselves. If no bit has changed, or if the original value remains unchanged, the SYNDROME[12:0] will be zero. However, if any bit changes—whether it's a data bit or an ECC bit—the position of the error is indicated by the SYNDROME[11:0]. When two bits are corrupted, SYNDROME[12] will be zero, while the remaining bits will be non-zero. If more than two bits change, the syndrome becomes undefined, and no reliable correction can be made.
When one or two bits are affected, the FRAME_ECC module can assert an error output. To enable this functionality, the FRAME_ECC_VIRTEX6 primitive must be instantiated in the user design and accessed through interfaces like SelectMAP, JTAG, or ICAP.
At the end of each readback frame, the syndrome_valid signal is asserted for one cycle of the readback clock (CCLK, TCK, or ICAP_CLK). The number of cycles required for readback depends on the interface used. Fixing the corrupted bit requires user intervention, as the FRAME_ECCE2 logic does not automatically correct errors. Therefore, the design must either store the original frame data or have a way to retrieve it for reloading.
The simplest operation involves reading a frame via ICAP and storing it in the module’s RAM. The frame address is generated as each frame is read. If an error is detected by the FRAME_ECC module, the readback stops, and the SYNDROME value is saved. If SYNDROME[12] is 0 and SYNDROME[11:0] is non-zero, the entire frame must be restored. If SYNDROME[12] is 1, the error bit can be located using SYNDROME[11:0]. Once corrected, the frame is written back to its original address, and readback resumes at the next frame address.
**Pin Descriptions:**
- **SYNDROMEVALID**: Output. Indicates when the syndrome is valid for sampling.
- **ECCERROR**: Output. Indicates whether an error was detected based on the syndrome.
- **SYNDROME[12:0]**: Output. Contains the syndrome value that identifies the type and location of the error.
- **CRCERROR**: Output. Indicates a CRC error during readback.
- **FAR[25:0]**: Output. Frame address register value used for SEU correction and ICAP applications.
- **SYNWORD[6:0]**: Output. Indicates the word address within the frame where the error occurred.
- **SYNBIT[4:0]**: Output. Indicates the specific bit position within the word where the error occurred.
- **ECCERRORSINGLE**: Output. Indicates a single-bit ECC error.
For SSIT devices, FRAME_ECCE2 is available across all SLRs. It is recommended to use this component in each SLR to ensure comprehensive error checking. If only one FRAME_ECC instance exists without layout constraints, it will be placed in the main SLR by default.
Integrated Energy solution with solar power, wind power, battery energy storage system, and diesel and gas generators. application for mobile power porter, household ESS sysytem with battery energy and solar PV unit. peak load for induatial and grid application.
solar power, battery, battery energy storage, CATL, PV Unit, Li(NiCoMn)O2 Battery, LiFePO4 Battery
Guangdong Superwatt Power Equipment Co., Ltd , https://www.swtgenset.com